This invention relates to frequency synthesizer devices and, in particular, to such devices using a phase-locked loop (PLL) comprising a voltage control oscillator (VCO), a phase comparator and a reference frequency oscillator.
A typical known frequency synthesizer using the PLL, as shown in FIG. 1, comprises a VCO 11, a variable frequency divider 12 which frequency divides the output frequency of the VCO 11, a reference frequency oscillator 13, and a phase comparator 14 which phase-compares between the output from the divider 12 and the reference frequency from the reference frequency oscillator 13 to apply the detected phase-difference signal to the VCO 11 as a control signal.
Generally, a DC amplifier 15 is provided between the output of the phase comparator 14 and the VCO 11 in order to amplify the phase-difference signal.
The variable frequency divider 12 is given a desired number information (N is a positive integer) by a suitable means and provides a signal having a frequency of 1/N of the input frequency value.
Accordingly, the output frequency f.sub.0 of the VCO 11 is maintained at a frequency of N times of the reference frequency f.sub.r. Therefore, a desired frequency can be selected by selecting the number of N to be given to the variable frequency divider.
Since the reference frequency oscillator is, usually, a crystal oscillator with a high frequency stability, the oscillating frequency of the VCO is stabilized.
The known frequency synthesizer has been used, for example, as a local oscillator in a FM receiver, because of the high frequency stability.
But the known frequency synthesizer has a disadvantage that the variable frequency divider is very expensive because it is required to have a high dividing precision.
Another disadvantage is that the frequency selection is hardly possible by a continuous operation such as rotating operation of a selection dial.